1. Field of the Invention
The present invention relates to a voltage comparator, an operational amplifier, and an analog-to-digital conversion circuit, having an analog-to-digital converter and a multistage pipeline (multi-step flush) structure, employing the voltage comparator and the operational amplifier.
2. Description of the Prior Art
Following the recent development of the digital processing technique for video signals, an analog-to-digital conversion circuit (A-D converter) for processing video signals is increasingly demanded. In general, a two-step flush (two-step parallel) system is widely employed for such an analog-to-digital conversion circuit for processing video signals, which must perform high-speed conversion.
However, the analog-to-digital conversion circuit of the two-step flush system cannot attain sufficient conversion accuracy for an enormous number of converted bits. To this end, an analog-to-digital conversion circuit having a multistage pipeline (multi-step flush) structure has been developed.
FIG. 14 is a block diagram showing the structure of a conventional analog-to-digital conversion circuit 101 having a multistage pipeline structure. The analog-to-digital conversion circuit 101 shown in FIG. 14 has a 10-bit four-stage pipeline structure.
Referring to FIG. 14, the analog-to-digital conversion circuit 101 includes a sample-and-hold circuit 102, a first-stage circuit 103, a second-stage circuit 104, a third-stage circuit 105, a fourth-stage circuit 106, a plurality of latch circuits 107 and an output circuit 108.
Each of the first-stage (initial stage) to third-stage circuits 103 to 105 comprises a sub A-D converter 109, a D-A converter 110 and a differential amplifier 111. The fourth-stage (final stage) circuit 106 comprises only a sub A-D converter 109.
The first-stage circuit 103 has a 4-bit structure, and the second- to fourth-stage circuits 104 to 106 have 2-bit structures respectively.
Operations of the analog-to-digital conversion circuit 101 are now described. The sample-and-hold circuit 102 samples an analog input signal Vin and holds the same for a constant time. The analog input signal Vin outputted from the sample-and-hold circuit 102 is transferred to the first-stage circuit 103.
In the first-stage circuit 103, the sub A-D converter 109 A-D converts the analog input signal Vin. The sub A-D converter 109 transfers the result of A-D conversion, i.e., a high order 4-bit digital output (2.sup.9, 2.sup.8, 2.sup.7, 2.sup.6) to the D-A converter 110 while transferring the same to the output circuit 108 through four latch circuits 107. The differential amplifier 111 amplifies the difference between the result of D-A conversion of the D-A converter 110 and the analog input signal Vin. The differential amplifier 111 transfers its output to the second-stage circuit 104.
The second-stage circuit 104 performs operations similar to those of the first-stage circuit 103 on the output from the differential amplifier 111 of the first-stage circuit 103. The third-stage circuit 105 performs operations similar to those of the first-stage circuit 103 on an output from the differential amplifier 111 of the second-stage circuit 104. The second-stage circuit 104 provides an intermediate high order 2-bit digital output (2.sup.5, 2.sup.4), while the third-stage circuit 105 provides an intermediate low order 2-bit digital output (2.sup.3, 2.sup.2).
In the fourth-stage circuit 106, the sub A-D converter 109 A-D converts an output from the differential amplifier 111 of the third-stage circuit 105, to provide a low order 2-bit digital output (2.sup.1, 2.sup.0).
The digital outputs from the first- to fourth-stage circuits 103 to 106 simultaneously reach the output circuit 108 through the respective latch circuits 107. In other words, the latch circuits 107 are adapted to synchronize the digital outputs from the circuits 103 to 106 with each other.
The output circuit 108 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction, if necessary.
Thus, in each of the first- to third-stage circuits 103 to 105 of the analog-to-digital conversion circuit 101, the differential amplifier 111 amplifies the difference between the analog input signal Vin or the output from the differential amplifier 111 of the precedent circuit 103 or 104 and the result of D-A conversion of the digital output thereof.
Even if the number of converted bits is increased to reduce the least significant bit (LSB), therefore, the resolution of comparators forming each sub A-D converter 109 can be substantially improved for attaining sufficient conversion accuracy.
Following the recent speed increase of electronic apparatuses, a higher conversion speed is required to analog-to-digital converters. In order to increase the conversion speed of the aforementioned conventional analog-to-digital conversion circuit 101, the GB product (gain-bandwidth product) of an operational amplifier forming each differential amplifier 111 must be increased. However, improvement of the GB product of the operational amplifier is limited. Therefore, it is difficult to further increase the conversion speed of the analog-to-digital conversion circuit 101.
As hereinabove described, the A-D converter of each circuit is referred to as the sub A-D converter 109, to be distinguished from the overall analog-to-digital conversion circuit 101. A total parallel comparison (flush) system which can perform high-speed conversion is employed for the sub A-D converter 109. The sub A-D converter 109 includes a plurality of comparators comparing an input voltage with a plurality of reference voltages. Each comparator is formed by a differential voltage comparator.
FIG. 15 is a circuit diagram of a conventional differential voltage comparator.
Referring to FIG. 15, a differential amplification circuit 10 includes P-channel MOS field-effect transistors (hereinafter referred to as PMOS transistors) 1 and 2, N-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors) 3 and 4 and a constant current source 7.
The PMOS transistors 1 and 2 are connected between a node ND and output nodes NO1 and NO2 respectively. The NMOS transistors 3 and 4 are connected between the output nodes NO1 and NO2 and a node NS respectively.
The node ND is supplied with a power supply voltage V.sub.DD, while the node NS is grounded through the constant current source 7. The PMOS transistors 1 and 2 are supplied with a bias voltage VB in the gates thereof respectively. The gates of the NMOS transistors 3 and 4 are connected to input nodes NA and NB respectively.
The input nodes NA and NB are connected to nodes N1 and N2 through capacitors 5 and 6 respectively. Switches SW11 and SW21 are connected between the input nodes NA and NB and the output nodes NO1 and NO2 respectively. Switches SW12 and SW13 are connected in parallel with the node N1, while switches SW22 and SW23 are connected in parallel with the node N2.
The switches SW12 and SW13 are supplied with input voltages V.sub.1 (+) and V.sub.2 (+) in input ends thereof respectively, while the switches SW22 and SW23 are supplied with input voltages V.sub.1 (-) and V.sub.2 (-) in input ends thereof respectively. Output voltages V.sub.0 (+) and V.sub.0 (-)are derived from the output nodes NO1 and NO2 respectively.
FIG. 16 is adapted to illustrate operations of the differential voltage comparator shown in FIG. 15.
First, the switches SW11, SW21, SW12 and SW22 are moved to ON, while the switches SW13 and SW23 are moved to OFF. At this time, differential input voltages between the input nodes NA and NB and between the output nodes NO1 and NO2 are 0 V.
Then, the switches SW11 and SW21 are moved to OFF, and thereafter the switches SW12 and SW22 are moved to OFF, while the switches SW13 and SW23 are moved to ON. Thus, voltages of the input nodes NA and NB change by V.sub.2 (+)-V.sub.1 (+)and V.sub.2 (-)-V.sub.1 (-) respectively. The difference between the input voltages V.sub.1 (+) and V.sub.2 (+) is referred to as a differential input voltage .DELTA.V(+), and that between the input voltages V.sub.1 (-) and V.sub.2 (-) is referred to as a differential input voltage .DELTA.V(-).
The differential amplification circuit 10 compares the differential input voltages .DELTA.V(+) and .DELTA.V(-) with each other, so that one of the output voltages V.sub.0 (+) and V.sub.0 (-) from the output nodes NO1 and NO2 changes toward the power supply voltage V.sub.DD and the other one changes toward the ground potential. Thus, the differential output voltage between the output nodes NO1 and NO2 changes to a positive or negative side.
In the differential voltage comparator shown in FIG. 15, each of the switches SW11 to SW13 and SW21 to SW23 is generally formed by a CMOS switch. FIGS. 17(a) and 17(b) are circuit diagrams of such a CMOS switch SW.
The switch SW shown in FIG. 17(a) is formed by a PMOS transistor 501 and an NMOS transistor 502, as shown in FIG. 17(b). The PMOS and NMOS transistors 501 and 502 are supplied with complementary control signals SA and SB in the gates thereof respectively.
In such a CMOS switch SW, parasitic capacitances Cs are present between the gates and sources and between the gates and drains of the PMOS and NMOS transistors 501 and 502. Therefore, switching noise depending on an input voltage in an ON or OFF state of the CMOS switch SW is transmitted through capacitive coupling of the parasitic capacitances Cs.
In the differential voltage comparator shown in FIG. 15, such switching noise causes noise n in the differential input voltage between the input nodes NA and NB, as shown in FIG. 16. Thus, the differential output voltage between the output nodes NO1 and NO2 temporarily changes on the basis of the noise n and thereafter changes to indicate the essential result of comparison. Consequently, it takes time to stabilize the differential output voltage between the output nodes NO1 and NO2 in the state indicating the essential result of comparison, and hence a subsequent circuit receiving the output signals V.sub.0 (+) and V.sub.0 (-) of the differential voltage comparator cannot obtain the result of comparison in a short time. Therefore, the speed of an analog-to-digital conversion circuit employing such a differential voltage comparator cannot be increased.